Start with an agreed rule matrix

List permitted via spans and combinations, conductor widths, copper clearances, land geometry, and relevant mask requirements. Tie each entry to the proposed stack and copper construction. Record whether a value is a nominal design input, a permitted adjustment range, or a finished acceptance requirement.

Altium's DFM discussion describes the problem of receiving manufacturing constraints after layout is advanced. Resolve the high-impact rules before routing the dense region, so the first successful escape is also a candidate for fabrication.

Use explicit scope and priority

A local fine-line exception should apply only where needed. Check that a broader default rule does not override it, and that the exception does not accidentally apply across the board. Name rules by their physical purpose so another engineer can understand why they exist.

For an illustrative BGA region, separate the short escape rule from the wider routing rule used outside the package. Define the boundary and any electrical transition requirements; do not rely on manual memory to restore widths later.

Check combinations the tool may not understand

Some important constraints concern a sequence of features: stacked microvias, a microvia over another via type, local copper balance, or return-path continuity. Determine which are enforced automatically and which require a documented review. A clean generic DRC report does not establish coverage of unconfigured or unsupported checks.

  • Audit the via types actually used in the board.
  • Review every accepted rule waiver and its reason.
  • Check source CAD against the released stack drawing.
  • Repeat affected checks after material, layer, or pad changes.

Release the rule basis with the design

Retain the approved matrix and manufacturing responses with the board revision. When feedback changes a pad or clearance, update both the layout and the rule that controls future edits. Otherwise, the next reroute can recreate the exact condition that was corrected during fabrication review.

DESIGN NOTE / SCHEMATIC

Adjacent-layer access, one connection at a time

Signal copper

Dielectric · geometry + material

Reference copper

Core or build-up dielectric

Signal copper

Illustrative only. Copper thickness, dielectric construction and via spans require a reviewed stackup.

Common questions

Does a zero-error DRC report prove manufacturability?

No. It proves that configured checks found no violations. Missing constraints and process interactions still require review.

Should the smallest capability be the default rule?

No. Use appropriate margin where space permits, and apply demanding rules only to regions that need them.

References & further reading

Method & assumptions · General design guidance. Validate the proposed construction and acceptance criteria for your project.