Resources / EXPLORE THE LIBRARY
HDI Engineering Resource Library
Prepare consistent fabrication data, agree on stackups and test evidence, and manage changes from prototype to production. These resources are organized around handoff decisions that can delay or weaken a manufacturing release.
Close the gap between CAD and fabrication.
Use the searchable directory to find a guide or tool. Start with the RFQ checklist for an early enquiry, then use stackup approval and first-article guidance as the design moves toward production.
All guides & tools
HDI Stackup Explorer
See how microvia access changes between 1+N+1, 2+N+2 and any-layer constructions.
02 / ToolsMicrovia Aspect Ratio Calculator
Calculate dielectric depth divided by finished hole diameter with clear units and manufacturing caveats.
03 / ToolsBGA Escape Geometry Calculator
Check how many straight traces geometrically fit between adjacent BGA pads, including edge clearance.
04 / ToolsMicrostrip Impedance Estimator
Explore single-ended microstrip impedance as trace width, dielectric height and Dk change.
05 / ToolsHDI Material Selection Tool
Build a material-family shortlist from loss, thermal exposure and interconnect requirements.
06 / ToolsPCB Propagation Delay Calculator
Estimate trace delay and the delay contribution of length mismatch using effective permittivity.
07 / ToolsHDI Cost Complexity Review
Identify fabrication and qualification items that deserve line-by-line discussion in an HDI quotation.
08 / ToolsHDI DFM Release Checklist
Record which stackup, via, material, impedance and manufacturing data checks have evidence before release.
09 / ToolsHDI PCB RFQ Brief Builder
Create a downloadable HDI manufacturing brief and continue to an external quotation service.
10 / FundamentalsAny-Layer PCB: Plan the Connections Before the Layers
Understand any-layer HDI, where it helps dense routing, and what to define before choosing an ELIC construction.
11 / FundamentalsHDI PCB: Choose Density Where the Design Needs It
A practical introduction to HDI printed circuit boards, covering routing demand, manufacturing constraints, and technology selection.
12 / ManufacturingHDI PCB Manufacturing: From Stack Definition to Acceptance
Plan an HDI manufacturing release around construction, process dependencies, inspection, and measurable acceptance requirements.
13 / ManufacturingAny-Layer PCB Manufacturing: Control Every Interconnect Stage
Review an any-layer manufacturing proposal through its via map, process sequence, material controls, and qualification evidence.
14 / ManufacturingHDI Prototypes: Build an Experiment with a Clear Decision
Use an HDI prototype to resolve routing, assembly, electrical, and manufacturing uncertainties before a production commitment.
15 / ManufacturingHDI Production: Preserve the Qualified Construction
Move from an HDI prototype to repeat production using a controlled baseline, representative evidence, and change management.
16 / ManufacturingSequential Lamination: Read the Board as a Build Sequence
Understand why HDI via access, material selection, and process stages must be planned together in a sequentially laminated board.
17 / ManufacturingLaser Drilling for HDI: Specify the Result, Review the Process
Define laser microvia geometry, landing conditions, material compatibility, and inspection requirements for an HDI release.
18 / ManufacturingCopper-Filled Microvias: Define the Structure Behind the Pad
Review copper-filled microvias through interface quality, surface condition, geometry, and the evidence needed for their intended use.
19 / ManufacturingVia-in-Pad: Coordinate Routing Space and Assembly Surface
Decide when via-in-pad is useful and define the via treatment, finished land, and assembly review that the design needs.
20 / ManufacturingFine-Line Etching: Keep Geometry and Copper Thickness Together
Plan fine-line HDI routing with finished copper geometry, local density, impedance requirements, and manufacturing tolerances.
21 / ManufacturingHDI Registration Tolerance: Budget the Landing Margin
Evaluate via-to-land registration with radial margin, dimensional variation, and layer-pair-specific manufacturing assumptions.
22 / ManufacturingHDI Electrical Testing: Define Coverage and Conditions
Separate bare-board connectivity testing, impedance verification, and stressed interconnect evaluation in an HDI acceptance plan.
23 / ManufacturingMicrosection Analysis: Ask a Structural Question First
Use microsections to examine HDI geometry and interfaces while accounting for sampling, preparation, and interpretation limits.
24 / ManufacturingMicrovia Reliability: Match Evidence to the Actual Structure
Build a microvia reliability review around geometry, materials, interfaces, assembly exposure, and representative performance testing.
25 / ManufacturingHDI Cost Drivers: Compare Complete Construction Choices
Assess HDI cost through process stages, usable panel area, feature combinations, materials, and acceptance requirements.
26 / DesignELIC vs Conventional HDI: Compare Reachable Routing Space
Compare any-layer ELIC and conventional HDI through required layer access, package escape, manufacturing complexity, and verification.
27 / DesignHDI vs Standard PCB: Test the Escape Before Choosing
Compare conventional and HDI PCB approaches using package escape, reference planes, board area, and manufacturing requirements.
28 / DesignStacked vs Staggered Microvias: Trade Footprint for Routing Freedom
Compare stacked and staggered microvia paths through area, intermediate routing, reference continuity, and representative reliability evidence.
29 / DesignBlind vs Buried Vias: Define Access and Construction Separately
Understand blind and buried via terminology, then map each connection to a practical manufacturing sequence and layout rule.
30 / DesignMicrovia Aspect Ratio: Calculate It with Agreed Dimensions
Use depth-to-diameter ratio as an HDI screening calculation while checking measurement convention, taper, tolerances, and process approval.
31 / Design1+N+1 HDI Stackup: Make One Build-Up Level Count
Plan a 1+N+1 HDI stack around first-level escape, central routing access, reference continuity, and a complete via map.
32 / Design2+N+2 HDI Stackup: Plan the Intermediate Layer
Design a two-level HDI build-up with explicit stacked or staggered transitions, intermediate routing, and central structure access.
33 / Design3+N+3 HDI Stackup: Justify the Third Access Level
Review a three-level HDI build-up through complete escape paths, interface combinations, reference changes, and qualification scope.
34 / DesignAny-Layer Stackup: Design a Network of Legal Transitions
Plan an any-layer stack with explicit transition paths, reference roles, material constraints, and controlled CAD definitions.
35 / Design6-Layer HDI Stackup: Protect the Reference Budget
Evaluate a six-layer HDI board through limited plane capacity, package escape, power distribution, and central-layer access.
36 / Design8-Layer HDI Stackup: Choose Access Depth or Central Capacity
Compare eight-layer HDI architectures by build-up depth, central routing resources, escape constraints, and reference continuity.
37 / Design10-Layer HDI Stackup: Organize Interface and Power Domains
Plan ten-layer HDI by assigning interface routes, reference layers, power distribution, and construction-specific transitions.
38 / Design12-Layer HDI Stackup: Control Complexity by Functional Region
Review a twelve-layer HDI design through functional routing budgets, interconnect combinations, materials, and verification scope.
39 / DesignStackup Symmetry: Review Materials, Copper, and Pattern Together
Evaluate PCB stack symmetry beyond layer count, including dielectric construction, copper thickness, material pairing, and local pattern balance.
40 / DesignSkip Microvias: Review the Full Depth and Intermediate Layer
Evaluate skip microvias as specific manufactured structures, including depth, intermediate copper, target geometry, and alternatives.
41 / DesignHDI Design Rules: Encode the Approved Construction
Build HDI CAD constraints around layer pairs, copper construction, complete via combinations, local exceptions, and release checks.
42 / DesignPads and Antipads: Balance Landing Margin and Plane Continuity
Select HDI capture pads, target lands, and antipads using manufacturing margin, electrical clearance, routing space, and reference behavior.
43 / DesignCopper Balance: Review Local Density Without Disturbing the Circuit
Assess copper distribution across HDI layers and regions, then coordinate balancing changes with electrical and manufacturing requirements.
44 / MaterialsFR-4 for HDI PCBs: Select a Construction, Not Just a Grade
Choose FR-4 for HDI using the build-up geometry, reflow exposure, channel loss, and verified construction data.
45 / MaterialsHigh-Tg FR-4: What It Does and What It Does Not Establish
Use Tg alongside expansion, decomposition, assembly exposure, and interconnect validation when selecting HDI materials.
46 / MaterialsLow-Loss Laminates for HDI: Spend the Channel Budget Deliberately
Compare low-loss PCB materials using channel length, copper profile, geometry, and a consistent simulation basis.
47 / MaterialsDk and Df: Use the Values That Match the PCB Model
Interpret dielectric constant and loss tangent with frequency, test method, glass construction, and modeling purpose.
48 / MaterialsGlass Weave and Differential Skew in HDI Routing
Review glass construction, route orientation, and channel symmetry before treating geometric length matching as timing closure.
49 / MaterialsCopper Roughness: A Material Choice Inside the Loss Model
Specify copper profile and treatment together with dielectric properties when evaluating high-speed HDI channels.
50 / MaterialsCTE and Z-Axis Expansion: Review the Whole Thermal Excursion
Relate laminate expansion to plated holes, microvia structures, and the real assembly and operating temperature history.
51 / MaterialsPrepreg Resin Content: Plan Fill, Thickness, and Electrical Behavior
Review prepreg resin content with copper distribution, pressed thickness, glass construction, and impedance requirements.
52 / MaterialsLaser-Drillable Dielectrics: Define the Complete Microvia Process
Evaluate build-up dielectrics through laser opening, cleaning, metallization, and final via geometry rather than a label.
53 / MaterialsHalogen-Free PCB Materials: Specify Chemistry and Performance Separately
Select a declared halogen-free laminate while preserving HDI construction, electrical behavior, and assembly requirements.
54 / MaterialsIsola I-Speed for HDI: Construction and Release Checklist
Evaluate I-Speed laminate and prepreg using construction tables, copper options, channel models, and process evidence.
55 / MaterialsIsola I-Tera MT40: Review the Exact Laminate and Bonding Build
Plan an I-Tera MT40 HDI stackup with construction-specific electrical data and explicit processing review.
56 / MaterialsPanasonic MEGTRON: Specify the Series, Grade, and Copper
Choose a MEGTRON construction with the exact product designation, dielectric build, copper option, and channel requirement.
57 / MaterialsRogers Hybrid Stackups: Control the Interfaces Between Materials
Evaluate a Rogers hybrid PCB through field distribution, bonding compatibility, symmetry, and the actual build-up sequence.
58 / MaterialsPCB Material Substitution: Approve the Changed Construction
Use an engineering change checklist for laminate substitutions covering impedance, loss, geometry, processing, and evidence.
59 / MaterialsMoisture and Storage: Preserve the State of Materials and Bare Boards
Separate prepreg handling from finished-board storage and keep moisture exposure tied to the correct material instructions.
60 / Signal integrityControlled Impedance: Turn a Target into a Manufacturable Geometry
Define impedance by layer, reference plane, trace geometry, material inputs, tolerance, and an agreed coupon plan.
61 / Signal integrityMicrostrip vs Stripline: Choose the Route and Its Reference Together
Compare outer and embedded transmission lines using access, dielectric environment, references, and channel transitions.
62 / Signal integrityDifferential Pairs: Control Symmetry Through the Entire Channel
Design differential pairs with consistent geometry, matched environments, reference continuity, and intentional transitions.
63 / Signal integritySignal Return Paths: Review the Copper Beneath the Route
Identify return-current continuity across HDI escapes, plane voids, connectors, and layer changes before routing release.
64 / Signal integrityVia Stubs: Find Unused Barrel Before It Consumes Channel Margin
Identify via stubs from actual layer usage and compare routing, backdrilling, and blind-via options for the channel.
65 / Signal integrityBackdrilling vs Microvias: Choose by Escape Geometry and Channel Needs
Compare controlled-depth drilling and HDI via structures using residual stubs, routing clearance, lamination, and verification.
66 / Signal integrityCrosstalk in HDI: Inspect the Escape and Vertical Transitions
Manage coupled noise through spacing, reference proximity, parallel length, via geometry, and realistic aggressor scenarios.
67 / Signal integrityInsertion Loss: Measure the Channel You Intended to Model
Build an insertion-loss budget that separates line attenuation, transitions, launches, and material assumptions.
68 / Signal integrityLength Matching: Close the Timing Path, Not Just the CAD Number
Use path definitions, package delay, layer-dependent propagation, and restrained tuning to meet interface timing requirements.
69 / Signal integrityPower Integrity for HDI: Design the Supply Path from Regulator to Package
Review DC drop, transient response, plane geometry, decoupling, and the package boundary as a connected power network.
70 / Signal integrityDecoupling Layout: Shorten the Complete Power-and-Return Loop
Place capacitors using connection inductance, via access, power-plane geometry, and device-specific requirements.
71 / Signal integrityReference-Plane Transitions: Give Return Current a Defined Route
Review old and new reference conductors at every layer change and avoid treating all stitching connections as equivalent.
72 / DesignBGA Fanout: Prove the Escape Before Choosing the HDI Stack
Plan package escape by signal groups, routing corridors, via access, references, and power connections before committing layer count.
73 / Design0.4 mm BGA Escape: Budget Every Pad, Opening, and Clearance
Evaluate 0.4 mm pitch BGA fanout with exact package lands, tolerance-aware routing, via processing, and assembly review.
74 / Design0.5 mm BGA Escape: Compare Dogbone and Microvia Routes
Evaluate 0.5 mm BGA routing with package-specific pads, tolerance margins, via lands, references, and layer access.
75 / DesignSolder-Mask Clearance: Review Openings and Webs as Real Geometry
Set mask openings using package lands, registration, minimum webs, via treatment, and the final exported manufacturing layers.
76 / DesignThermal Vias: Connect Heat to a Useful Spreading Structure
Design thermal via arrays with package electrical requirements, copper spreading, solder control, and system cooling in view.
77 / DesignHDI DFM Review: Close the Gaps Between CAD and the Proposed Build
Review the stackup, via sequence, escape geometry, mask, electrical requirements, and release data as one HDI manufacturing definition.
78 / ApplicationsHDI PCB Design for Smartphones
Plan smartphone HDI routing around processor escape, cameras, RF zones, battery space and assembly access before selecting any-layer construction.
79 / ApplicationsHDI PCB Planning for Wearable Electronics
Balance wearable PCB size, battery life, sensing, antenna space and mechanical constraints with a practical HDI design review.
80 / ApplicationsHDI PCB Design for Camera Modules
Review camera module sensor placement, image interface routing, power noise, optical alignment and connector escape before PCB release.
81 / ApplicationsHDI PCB Considerations for Medical Electronics
Organize medical electronics PCB requirements around sensing, isolation, traceability, inspection and documented design verification.
82 / ApplicationsHDI PCB Design for Hearing Devices
Coordinate miniature hearing device PCB layout with microphones, acoustic paths, battery space, charging contacts and assembly verification.
83 / ApplicationsHDI PCB Design for Industrial IoT Nodes
Plan compact industrial IoT boards around sensors, radio placement, external wiring, service access and operating environment.
84 / ApplicationsHDI PCB Planning for Automotive ADAS Electronics
Review ADAS PCB density together with sensor interfaces, processor power, thermal integration, diagnostics and change traceability.
85 / ApplicationsHDI PCB Considerations for Automotive Radar
Coordinate radar PCB antenna geometry, RF transitions, digital escape, material selection and mechanical verification.
86 / ApplicationsHDI PCB Design for 5G Modules
Plan 5G module boards around radio architecture, power bursts, thermal paths, host interfaces and controlled RF geometry.
87 / ApplicationsHDI PCB Design for RF Modules
Evaluate compact RF PCB stackups, grounding, matching networks, shielding and prototype measurements without assuming density guarantees performance.
88 / ApplicationsHDI PCB Planning for AI Accelerator Boards
Review AI accelerator PCB escape, power delivery, memory, high speed links and cooling as one integrated architecture.
89 / ApplicationsHDI PCB Design for Edge Computing Systems
Choose edge computer board architecture with module interfaces, peripheral routing, power sequencing, cooling and recovery access in view.
90 / ApplicationsHDI PCB Planning for Network Switches
Allocate switch PCB channel loss, connector escape, power distribution and thermal space before selecting HDI materials and via structures.
91 / ApplicationsHDI PCB Design for Optical Transceivers
Coordinate optical transceiver PCB electrical channels, optical alignment, cage mechanics, heat flow and manufacturing evidence.
92 / ApplicationsHDI PCB Design for Robotics Electronics
Plan robotics PCB density with motor current paths, sensing, computation, cables, maintenance and mechanical mounting in view.
93 / ApplicationsHDI PCB Planning for Drone Electronics
Balance drone controller density with motion sensing, radio placement, motor electronics, mounting and prototype test access.
94 / ApplicationsHDI PCB Design for Miniature Sensors
Design small sensor PCBs with mechanical strain, thermal gradients, reference routing, calibration and assembly handling in mind.
95 / ApplicationsHDI PCB Design for USB-C Devices
Plan USB-C connector escape, data lanes, power paths, protection and mechanical attachment using explicit interface requirements.
96 / ResourcesHDI PCB RFQ Checklist
Prepare an HDI request for quotation with clear construction, via spans, tolerances, quantities, acceptance requirements and engineering questions.
97 / ResourcesHDI PCB Fabrication Drawing Guide
Build a fabrication drawing that identifies the HDI stackup, via structures, finished dimensions, impedance requirements and document precedence.
98 / ResourcesHDI PCB Drill File Requirements
Check drill formats, coordinates, plated status, layer spans and slot definitions for a clear HDI fabrication data release.
99 / ResourcesGerber, ODB++ and IPC-2581 for HDI Data Handoff
Choose and verify PCB manufacturing exchange formats with clear layer intent, drill spans, revision control and supplier compatibility.
100 / ResourcesHDI PCB Stackup Approval Checklist
Approve HDI layer construction with material identity, dielectric thickness, copper, via spans, impedance assumptions and change limits recorded.
101 / ResourcesPCB Impedance Coupon Requirements
Specify representative impedance coupons, measurement conditions, traceability and acceptance reports for an HDI PCB order.
102 / ResourcesHDI Microvia Test Coupon Planning
Plan representative microvia test structures with agreed thermal exposure, measurement, traceability and acceptance criteria.
103 / ResourcesHDI PCB First Article Inspection Checklist
Review the first HDI PCB build with revision checks, dimensional evidence, construction records, test reports and documented dispositions.
104 / ResourcesMoving an HDI PCB from Prototype to Production
Transfer HDI prototype lessons into a controlled production baseline with construction, assembly, test and change evidence intact.
105 / ResourcesHDI PCB Supplier Qualification Questions
Evaluate an HDI supplier with construction specific evidence, process scope, traceability, change control and clear acceptance responsibilities.
106 / ResourcesWhat Determines HDI PCB Lead Time?
Understand HDI scheduling through engineering release, material readiness, sequential operations, inspection and agreed delivery assumptions.
107 / ResourcesEngineering Change Control for HDI PCBs
Control HDI design and manufacturing changes with clear baselines, impact review, file regeneration, supplier approval and verification evidence.
108 / ResourcesHDI PCB Glossary for Design and Purchasing
Understand practical HDI terminology for via structures, buildup layers, stackups, coupons and manufacturing release discussions.
109 / ResourcesCommon HDI PCB Questions Before Design Release
Answer practical HDI questions about need, cost, layer count, supplier review, reliability evidence and complete manufacturing files.