Diagnose the bottleneck
If pins cannot escape the package region, additional local access may help. If the escape is complete but long routes compete for channels across the board, more central routing resources or a placement change may be more useful. Record which problem remains before changing architecture.
A route should count as escaped only when it reaches a layer and channel from which its destination is practical. A collection of short stubs outside the package does not demonstrate that the whole board will route.
Compare two sketches at equal maturity
Create one realistic escape region for each candidate architecture. Use approved land dimensions, clearances, and via combinations rather than idealized circles. Mark the layers consumed by reference and power duties so neither option receives an artificially generous routing budget.
| Illustrative architecture | Question to answer |
|---|---|
| 1+6+1 | Can one build-up level reach useful central channels? |
| 2+4+2 | Does the second access level justify less central layer capacity? |
| Another approved eight-layer construction | What exact connection constraint does it improve? |
Check the reference cost of escape
Inspect plane clearances beneath the package and around via fields. A densely perforated reference region may not behave like the continuous plane assumed in an early model. Keep the return path and nearby reference connections visible while routing the signal transitions.
Altium's stackup documentation supports defining layer materials and electrical properties together. Use one authoritative stack definition to keep the layout, impedance assumptions, and fabrication drawing aligned as the architecture evolves.
Decide using a complete routing sample
Include at least one demanding interface from component to destination, plus representative power connections. The preferred option should show sufficient margin for the remaining nets and later edits. If both candidates depend on unapproved structures, resolve the manufacturing issue before committing the rest of the placement and routing effort.
Adjacent-layer access, one connection at a time
Dielectric · geometry + material
Core or build-up dielectric
Illustrative only. Copper thickness, dielectric construction and via spans require a reviewed stackup.
Common questions
Does an eight-layer stack imply two build-up levels?
No. Layer count and build-up depth are separate choices. The drawing and via map must state the actual construction.
Which option provides more signal layers?
That depends on reference and power allocation as well as access. Count the layers that can carry the required routes in the proposed design.
References & further reading
Method & assumptions · General design guidance. Validate the proposed construction and acceptance criteria for your project.