Density is local before it is global

A board may have ample empty space and still need HDI beneath one package. The restriction is often the narrow path between neighboring lands, the number of signals trapped inside the array, or the space consumed by through-via pads on inner layers. Identify that restriction before reducing the rules across the entire layout.

Use ordinary widths and clearances where possible. Local exceptions should have a reason, a defined boundary, and a manufacturing review rather than becoming the default for every net.

Evaluate the package and the board together

Package pitch alone cannot select a PCB technology. Ball placement, depopulated regions, power distribution, pin assignment, and escape direction all affect what can be routed. NXP publishes examples of non-HDI layouts for specific WLCSP devices, illustrating why a small package is not sufficient evidence that HDI is mandatory.

For your device, use its own land-pattern and layout information. A successful escape on a different component is useful inspiration, but not a validated footprint or routing rule.

Choose the least complex workable construction

Build an initial escape study around the hardest component. Try an approved conventional construction, then a single build-up level, and only add deeper access if the routes require it. Keep placement, net grouping, reference needs, and board dimensions comparable so the alternatives answer the same problem.

  • Count blocked routes rather than merely counting available layers.
  • Keep ground continuity visible during the escape study.
  • Check power delivery before claiming the package is fully routed.
  • Compare room for assembly and test alongside wiring density.

Turn the choice into manufacturing data

Record the selected construction with named drill pairs and a stack drawing. Include finished-feature requirements and an inspection plan appropriate to the product. A statement such as 'HDI board' leaves too much unresolved for reliable quotation, fabrication, or comparison between suppliers.

DESIGN NOTE / SCHEMATIC

Adjacent-layer access, one connection at a time

Signal copper

Dielectric · geometry + material

Reference copper

Core or build-up dielectric

Signal copper

Illustrative only. Copper thickness, dielectric construction and via spans require a reviewed stackup.

Common questions

Is every multilayer PCB an HDI PCB?

No. A multilayer board can use conventional through-hole interconnection. Layer quantity and interconnect architecture describe different aspects of the design.

Should I shrink every track after choosing HDI?

No. Preserve width and spacing margin outside the constrained regions. Finer geometry should solve a specific routing problem.

References & further reading

Method & assumptions · General design guidance. Validate the proposed construction and acceptance criteria for your project.