Signal integrity / EXPLORE THE LIBRARY
Signal Integrity in HDI PCBs
HDI can create compact transitions, but electrical performance still depends on the complete signal and return-current path. Explore impedance, loss, coupling, stubs, timing and power delivery as connected design decisions.
Keep the return path in the design.
Choose a guide around the symptom or constraint you need to resolve. Use the calculators to understand sensitivity to geometry, then move to an appropriate solver or measurement plan before committing production tolerances.
Explore signal integrity
Controlled Impedance: Turn a Target into a Manufacturable Geometry
Define impedance by layer, reference plane, trace geometry, material inputs, tolerance, and an agreed coupon plan.
02 / Signal integrityMicrostrip vs Stripline: Choose the Route and Its Reference Together
Compare outer and embedded transmission lines using access, dielectric environment, references, and channel transitions.
03 / Signal integrityDifferential Pairs: Control Symmetry Through the Entire Channel
Design differential pairs with consistent geometry, matched environments, reference continuity, and intentional transitions.
04 / Signal integritySignal Return Paths: Review the Copper Beneath the Route
Identify return-current continuity across HDI escapes, plane voids, connectors, and layer changes before routing release.
05 / Signal integrityVia Stubs: Find Unused Barrel Before It Consumes Channel Margin
Identify via stubs from actual layer usage and compare routing, backdrilling, and blind-via options for the channel.
06 / Signal integrityBackdrilling vs Microvias: Choose by Escape Geometry and Channel Needs
Compare controlled-depth drilling and HDI via structures using residual stubs, routing clearance, lamination, and verification.
07 / Signal integrityCrosstalk in HDI: Inspect the Escape and Vertical Transitions
Manage coupled noise through spacing, reference proximity, parallel length, via geometry, and realistic aggressor scenarios.
08 / Signal integrityInsertion Loss: Measure the Channel You Intended to Model
Build an insertion-loss budget that separates line attenuation, transitions, launches, and material assumptions.
09 / Signal integrityLength Matching: Close the Timing Path, Not Just the CAD Number
Use path definitions, package delay, layer-dependent propagation, and restrained tuning to meet interface timing requirements.
10 / Signal integrityPower Integrity for HDI: Design the Supply Path from Regulator to Package
Review DC drop, transient response, plane geometry, decoupling, and the package boundary as a connected power network.
11 / Signal integrityDecoupling Layout: Shorten the Complete Power-and-Return Loop
Place capacitors using connection inductance, via access, power-plane geometry, and device-specific requirements.
12 / Signal integrityReference-Plane Transitions: Give Return Current a Defined Route
Review old and new reference conductors at every layer change and avoid treating all stitching connections as equivalent.