Start with the physical cross-section
Analog Devices MT-094 explains the basic microstrip and stripline structures and the limitations of approximate impedance formulas. In a real board, also identify solder mask, unequal dielectric heights, adjacent copper, and material differences. An asymmetric embedded route is not the same geometry as an ideal symmetric stripline. Use a model that represents the actual cross-section before comparing widths or propagation delay. A layer name such as inner signal is not enough.
Compare access with the needed routing path
A surface route can connect nearby components without diving through the stack, and it is easier to access during debugging. An embedded route can provide a controlled environment between planes but requires suitable transitions from surface-mounted devices. Compare the whole path, including launch vias and any stubs. If moving a short route inward adds two difficult transitions, the theoretical advantage of the line structure may not produce a better channel overall.
Budget timing and loss for each segment
Do not use one delay-per-length assumption for mixed surface and embedded routing unless the model justifies it. Likewise, compare loss at equivalent impedance with the chosen conductor dimensions and dielectric system. A route may change width when it changes layers while remaining correctly impedance controlled. Keep those layer-specific dimensions in the CAD rules. When matching channels, compare the electrical paths rather than forcing identical visible lengths across different transmission-line structures.
Choose planes that survive the real layout
A stripline label does not guarantee continuous reference copper. Check splits, voids, antipads, and power islands along the entire route. For microstrip, examine nearby surface copper and component clearances that alter the modeled geometry. Make the layer assignment after these constraints are known. A practical review overlays signal routes on their reference layers and highlights every transition. That view often reveals a more useful improvement than changing all critical nets from one topology to another.
A continuous reference keeps the return path close
Dielectric · geometry + material
Core or build-up dielectric
Illustrative only. Copper thickness, dielectric construction and via spans require a reviewed stackup.
Common questions
Is stripline always lower loss?
No. The result depends on dielectric exposure, conductor dimensions, materials, and frequency. Compare complete structures at the required impedance.
Can I keep the same width when moving between microstrip and stripline?
Only if the calculated structures support it. Usually each layer needs its own approved geometry and the transition needs review.
References & further reading
Method & assumptions · General design guidance. Validate the proposed construction and acceptance criteria for your project.