Build an access map

Represent each copper layer as a destination and each permitted via span as a connection. Then define which connection sequences are allowed. Two individually legal spans may still form an unapproved stacked arrangement when used at the same location.

Use this map to review package escape and long-distance routing separately. The package region needs compact local access; the rest of the board needs predictable routing channels, reference continuity, and manageable transitions between functional blocks.

Assign planes before exploiting every layer

Any-layer access does not turn every copper layer into unrestricted signal routing space. Reserve the reference and power structures needed by the electrical design. If local escapes cross a plane region, review the resulting copper continuity and the path available to return current.

For an illustrative compact computing module, separate a dense processor escape from a quieter clock route. Giving both nets the shortest geometric path may put the clock through an unnecessarily complex transition. Route according to function as well as available access.

Keep the physical construction coherent

Choose dielectric thicknesses, copper assumptions, and material families with the manufacturing reviewer. A change made to improve one microvia ratio can alter the reference spacing or overall thickness. Track these dependencies rather than editing the stack table as a collection of independent cells.

  • Name each approved transition sequence and its intended use.
  • Identify critical routes that require electrical modeling.
  • Review symmetric material and copper construction where practical.
  • Document the qualification scope for the actual via combinations.

Constrain automation to the approved map

Cadence's HDI routing discussion describes tools that build sequences of vias while changing layers. Ensure the software's allowed transition list matches the manufacturing map. After routing, inspect the structures actually used, remove accidental combinations, and export the same definitions into the fabrication package. The released board should contain no unnamed exceptions.

DESIGN NOTE / SCHEMATIC

Adjacent-layer access, one connection at a time

Signal copper

Dielectric · geometry + material

Reference copper

Core or build-up dielectric

Signal copper

Illustrative only. Copper thickness, dielectric construction and via spans require a reviewed stackup.

Common questions

Does any-layer mean a single hole can connect any two layers?

No. Connections follow the chosen manufacturing architecture, often through combinations of approved short spans. Define the actual physical path.

Can the stack be finalized after routing?

Small refinements may be possible, but via access and electrical geometry should be agreed early. Late changes can invalidate many routes at once.

References & further reading

Method & assumptions · General design guidance. Validate the proposed construction and acceptance criteria for your project.