Compare access before counting layers
Draw the layers reachable from the hardest package pins using each option. A routing layer only helps if a legal transition can reach it without blocking neighboring signals or breaking the reference strategy. More total layers cannot compensate for an escape pattern that traps the inner pin rows.
Use the same package placement and net destinations in both studies. Otherwise, a better placement in one option can be mistaken for a benefit of its interconnect technology.
Identify the constraint ELIC removes
In an illustrative compact processor design, conventional build-up access might route the outer pin groups successfully but force long detours for the center groups. ELIC deserves evaluation if its additional access removes those detours while meeting the enclosure and electrical requirements. It is less persuasive when all required routes already fit with useful margin.
| Review question | Conventional HDI | ELIC / any-layer |
|---|---|---|
| Where is access needed? | Selected build-up regions | Broader layer-to-layer access |
| What should be compared? | Reachable channels and core transitions | Complete microvia paths and interfaces |
| What requires evidence? | Proposed construction | Proposed construction and added complexity |
Include the hidden work in the comparison
Both alternatives need a material and manufacturing review. Compare representative interconnect evidence, assembly exposure, test accessibility, and change-control needs. Do not assume that a compact electrical route is automatically the easiest structure to manufacture or qualify.
Cadence's stackup explanation provides the architecture terminology. Treat it as vocabulary for the comparison, while obtaining a project-specific construction from the fabricator. Names such as advanced HDI or any-layer are too broad to resolve acceptance requirements.
Make a decision that survives review
Present the proposed outline, layer access map, unresolved routes, and critical electrical paths for each option. Select the option only after the difficult regions have been demonstrated. Retain the rejected option's key tradeoffs so a later package or enclosure change can be evaluated without repeating the entire investigation.
Adjacent-layer access, one connection at a time
Dielectric · geometry + material
Core or build-up dielectric
Illustrative only. Copper thickness, dielectric construction and via spans require a reviewed stackup.
Common questions
Is ELIC always electrically better?
No. Electrical behavior depends on routing, reference continuity, geometry, and materials. Shorter physical transitions still need an appropriate return path and model.
Can conventional HDI use stacked microvias?
Yes, where the approved construction supports them. Stacking alone does not identify a complete board architecture as ELIC.
References & further reading
Method & assumptions · General design guidance. Validate the proposed construction and acceptance criteria for your project.