Count the connections that must leave each region
Mark unused balls, fixed high-speed pins, swappable signals, power groups, and ground connections on the package map. Count the routes that must cross each side of the escape boundary rather than assuming all balls are equivalent signals. AMD's BGA guidance identifies pin quantity, pad geometry, fixed pinouts, and fabrication technology as layer-count drivers. Use those categories to build a routing demand map before choosing a familiar stackup by habit.
Prove the narrowest corridor
For a proposed route between adjacent pads, compare the free gap with the trace width plus both clearances. Include the actual pad and via lands used on that layer, not only package ball diameter. Check diagonal corridors separately because their limiting neighbors differ. A geometric fit at nominal dimensions is a screening result, not production approval. Ask the fabricator to review tolerance, registration, and whether the intended line formation is compatible with the copper construction.
Reserve reference and power access
An escape that routes every signal but leaves no useful ground continuity or decoupling access is unfinished. Assign reference connections and power access while allocating signal layers. Review whether via antipads merge into a barrier beneath critical routes. Protect the shortest power-and-return paths where the package needs them. If adding another signal layer would require sacrificing a reference plane, compare the resulting electrical structure rather than counting that layer as a free routing resource.
Compare viable escapes as complete builds
Prepare a small set of alternatives, such as a conventional escape, a shallow build-up, and a more extensive HDI structure where needed. For each, record signal layers, via spans, lamination sequence, special pad processing, and remaining electrical exceptions. Route a representative dense quadrant far enough to demonstrate that the corridors connect to their destinations. Select the option with a workable manufacturing and assembly plan, then apply that approved geometry to the full package.
Adjacent-layer access, one connection at a time
Dielectric · geometry + material
Core or build-up dielectric
Illustrative only. Copper thickness, dielectric construction and via spans require a reviewed stackup.
Common questions
Does a fine-pitch BGA always require any-layer HDI?
No. The ball map, used signals, pad geometry, and routing destinations determine the needed access. Prove the escape before choosing a more complex build.
Can I decide layer count by ball count alone?
No. Fixed pins, power and ground allocation, available corridors, reference planes, and manufacturing technology all change the routing problem.
References & further reading
Method & assumptions · General design guidance. Validate the proposed construction and acceptance criteria for your project.