Follow the route after the first microvia

A surface escape can look complete when every package pad reaches the next layer. Continue the study from that layer to each net's destination. If the next layer is mostly reference copper, or deeper access consumes all available channels, the first transition has moved the bottleneck rather than solved it.

Define the central structure's allowed vias and routing roles at the same time as the outer build-up. The two regions must work as a single connection system.

Use the layer arithmetic correctly

For an illustrative eight-layer board, 1+6+1 accounts for all eight copper layers. It does not state whether the center uses buried vias, where power planes sit, or how many manufacturing operations are needed. A six-layer 1+4+1 example has the same build-up depth but a different central routing budget.

Cadence uses this family of shorthand to explain HDI architectures. Supplement it with a numbered cross-section and a via table so reviewers do not infer missing construction details from the notation.

Allocate references before the escape consumes them

Decide which layers provide reference continuity for the dense surface routes. Limited local escape routing on a nominal plane layer can change the return-path environment. Review that geometry explicitly rather than preserving a plane label that no longer describes the copper beneath the signals.

  • Trace the difficult inner package rows to real destinations.
  • Check power and ground access alongside signal escape.
  • Identify every permitted transition into the central structure.
  • Reserve room for test access before final component packing.

Know when to evaluate another architecture

If the remaining unrouted nets all need a second inward access level, compare a 2+N+2 option with placement or assignment changes. If the problem is simply insufficient long-distance routing area, a larger central structure or outline may be more direct. Diagnose the bottleneck before adding process complexity.

DESIGN NOTE / SCHEMATIC

Adjacent-layer access, one connection at a time

Signal copper

Dielectric · geometry + material

Reference copper

Core or build-up dielectric

Signal copper

Illustrative only. Copper thickness, dielectric construction and via spans require a reviewed stackup.

Common questions

Does 1+N+1 specify the total layer count?

Only after N is defined. Total copper layers equal N plus two; materials, thicknesses, and via details remain separate requirements.

Must the second layer be ground?

No universal assignment fits every design. Choose its role through escape, signal-reference, power, and manufacturing review.

References & further reading

Method & assumptions · General design guidance. Validate the proposed construction and acceptance criteria for your project.