Trace both sides of the capacitor connection

Analog Devices MT-101 discusses decoupling together with the parasitic behavior of capacitors and interconnections. Apply that principle by drawing the power-and-return loop from capacitor to device. A nearby capacitor can still have a poor connection if its ground via is distant or its power path detours around a plane void. Review both terminals in the layout. The best-looking placement on the component side may differ from the shortest electrical connection through the stack.

Use HDI access where it changes the loop

Short build-up vias can help reach an adjacent plane, but the benefit depends on where the device power and ground connections actually go. For a BGA, compare top-side perimeter placement with underside placement and the required via paths. Protect room for the most constrained capacitors during fanout planning. If signal escape consumes all access to the relevant power island, adding capacitance farther away may not solve the missing local connection.

Check component models and mounting together

Capacitance value, package, voltage bias, ESR, and mounting inductance all affect the network response. Do not assume different nominal values automatically cover different frequency ranges usefully. Use models appropriate to the selected components and examine the combined network. A smaller package may allow a better connection, but assembly and sourcing constraints also matter. Keep the selected part and its footprint linked in the review so a later package substitution does not invalidate the mounting assumptions.

Review shared connections and verification access

Several capacitors sharing one narrow copper neck or one return via may not provide the intended independent paths. Inspect the final pours, not only the routed traces, and confirm that thermal-relief settings have not created an unintended restriction. Plan measurement access that does not require a long probe ground lead. During validation, compare the rail response before changing components so that an observed improvement can be attributed to a specific placement, connection, or value change.

DESIGN NOTE / SCHEMATIC

A continuous reference keeps the return path close

Signal copper

Dielectric · geometry + material

Reference copper

Core or build-up dielectric

Signal copper

Illustrative only. Copper thickness, dielectric construction and via spans require a reviewed stackup.

Common questions

Is one capacitor per power pin a universal rule?

No. Follow device guidance and verify the resulting network. Package behavior, available planes, mounting geometry, and operating conditions affect the appropriate implementation.

Should every decoupling capacitor touch the IC footprint?

Physical proximity is useful only when it supports a short complete connection. Review the power and return paths through the actual stackup.

References & further reading

Method & assumptions · General design guidance. Validate the proposed construction and acceptance criteria for your project.