Start with the escape problem

Map the package pins that cannot reach their destinations using the proposed conventional stack. Include power and ground connections, because signal escape alone can make a layout look deceptively complete. Mark the required destination layer for each difficult pin group and identify where intermediate capture pads would block another route.

This connection map becomes the reason for choosing any-layer technology. If the difficult connections are confined to one outer build-up layer, a simpler HDI construction may provide the same usable board area.

Freedom still needs rules

Any-layer does not mean an unrestricted hole can be drilled between arbitrary finished layers. Each connection must correspond to a producible sequence, approved pad geometry, and supported material thickness. A chain of short connections and a single long hole are different structures even when their netlist endpoints match.

Write the allowed spans and combinations into the CAD rules. Review the complete transition, including reference-plane changes and unused copper, rather than approving each individual microvia in isolation.

Compare the system tradeoff

Consider an illustrative compact processor board whose inner package rows need several routing depths. An any-layer option may reduce lateral escape distance, but its extra process dependencies could outweigh the area saving if the enclosure still has unused space. Compare a slightly larger conventional HDI layout against the compact option before freezing the mechanical outline.

  • Measure board-area savings at the same component placement maturity.
  • Compare complete manufacturing sequences, not layer counts alone.
  • Include assembly exposure and reliability evidence in the decision.
  • Reserve room for test access and future package changes.

Define a reviewable release

Provide a numbered cross-section, via-span table, proposed materials, impedance requirements, and a description of expected assembly and service conditions. Request confirmation of the actual construction and acceptance plan. Treat any dimensions in early concept sketches as design inputs awaiting review, not advertised supplier capability.

DESIGN NOTE / SCHEMATIC

Adjacent-layer access, one connection at a time

Signal copper

Dielectric · geometry + material

Reference copper

Core or build-up dielectric

Signal copper

Illustrative only. Copper thickness, dielectric construction and via spans require a reviewed stackup.

Common questions

Does any-layer automatically reduce total cost?

No. Board area, routing effort, process complexity, qualification, and yield must be compared together. The smallest outline may not give the lowest product cost.

Must every connection use stacked microvias?

No. Choose each transition for its routing need and approved construction. Unnecessary transitions add complexity without improving the design.

References & further reading

Method & assumptions · General design guidance. Validate the proposed construction and acceptance criteria for your project.