Start from the exact package drawing
Confirm the package variant, ball map, recommended land pattern, and assembly notes. TI's 0.4 mm PoP application report is a useful example of close coordination between board design and assembly, but its dimensions belong to its documented package context. Use the current guidance for your selected component. Preserve the footprint source and revision so a later library update does not silently change the copper lands or solder-mask openings in a proven escape.
Make a nominal corridor calculation
For an illustrative geometry only, a 0.40 mm pitch with 0.24 mm circular copper lands leaves a 0.16 mm straight gap. A 0.06 mm trace with 0.05 mm clearance on either side consumes that entire gap. This arithmetic shows the absence of spare nominal space; it does not establish acceptable fabrication tolerances. Actual package recommendations and the chosen process may require different lands, mask openings, widths, and clearances. Review those together before accepting the route.
Treat via-in-pad as an assembly feature
If the escape uses an in-pad microvia, specify the intended filling, planarization, and copper-cap arrangement with the fabricator and assembler. Do not assume a solder-mask tent is interchangeable with a planar solderable land. Check the target pad and lower-layer routing corridor as well as the visible component pad. The via can solve top-layer access while creating a bottleneck on the next layer, especially where power, ground, and return connections compete for the same space.
Prototype the constrained region intentionally
Before completing all routing, review a representative escape section with production partners. Include mask webs, stencil assumptions, inspection access, copper distribution, and thermal exposure. Agree which evidence will demonstrate assembly quality and electrical continuity for the selected construction. If the proposed process is new, make the prototype answer that specific question. A successful coarse-pitch device elsewhere on the board does not validate the most constrained package region.
Adjacent-layer access, one connection at a time
Dielectric · geometry + material
Core or build-up dielectric
Illustrative only. Copper thickness, dielectric construction and via spans require a reviewed stackup.
Common questions
Is a trace between every pair of 0.4 mm pads always possible?
No. The answer depends on actual land sizes, mask strategy, line-and-space capability, and tolerance. Some escapes need another routing approach.
Does 0.4 mm pitch automatically require stacked microvias?
No. Evaluate the ball map and reachable routing layers. Use the simplest qualified structure that completes the escape and preserves electrical requirements.
References & further reading
Method & assumptions · General design guidance. Validate the proposed construction and acceptance criteria for your project.